I. Field of the Invention
The present invention relates to the digital measurement of an unknown input voltage and, more particularly, to a method and system for controlling the run-up (RU) portion of an integrating analog-to-digital (A/D) converter.
II. Related Art
A conventional integrating A/D converter is illustrated in FIG. 1. Generally, the integrating A/D converter converts an analog input voltage V.sub.IN into a digital signal, or an "integrator count." An operational amplifier (OP-AMP) 102 in combination with a capacitor C.sub.1 constitute an integrator 106. The integrator 106 receives the analog input voltage V.sub.IN and provides an output voltage V.sub.INT to a comparator 108. The comparator 108 compares V.sub.INT to a reference voltage, which oftentimes is ground, as shown in FIG. 1. The comparator 108 then feeds a comparator output voltage V.sub.C to control logic 110, which in turn controls a switch 112. The switch 112 can be controlled to provide either the input voltage V.sub.IN or a reference voltage V.sub.REF at any given instance. The reference voltage V.sub.REF can be positive or negative. The control logic 110 provides the integrator count, as indicated at a line 114.
In conventional dual slope integration, the input voltage V.sub.IN is applied to the input of the integrator 106 for a run-up (RU) interval of duration T, as indicated in FIG. 2. Moreover, a reference discharging voltage V.sub.REF is then applied to the integrator input during a run-down (RD) interval. The RD interval ends when the capacitor C.sub.1 is totally discharged. The duration t of the RD interval is measured, and the value of the input voltage V.sub.IN is calculated as follows: V.sub.IN =t*(V.sub.REF /T).
Integrating A/D converters are desirable because they essentially average the analog voltage over a short time period to provide a digital representation. In effect, the integrating A/D converter cancels or reduces noise during the period T.
The value of duration t is typically measured by counting (usually synchronous with the clock) during the RD interval. For a given counter rate, the sensitivity of the A/D converter increases with a decrease in the rate at which the discharge occurs. Therefore, sensitivity can be increased by decreasing the magnitude of V.sub.REF. However, the decreasing of V.sub.REF results in a slower response of the circuit, which is impractical in many instances.
The sensitivity can also be increased by increasing the maximum voltage V.sub.m of the integrator output voltage V.sub.INT for a fixed duration of the RU interval. An increase in V.sub.m is achieved by reducing the value of the input resistance R.sub.IN to increase the slope of the integrator output voltage V.sub.INT during the RU interval. However, for an OP-AMP integrator 106, the integrator output voltage V.sub.INT must be within the bounds of the OP-AMP power supply voltage limits.
As illustrated in FIG. 3, a large (steep) slope during the RU interval can be employed without exceeding the voltage of the power supply by imposing a saw-toothed response during the RU interval. Whenever the integrator output voltage V.sub.INT is detected as approaching a voltage V.sub.1, the reference voltage V.sub.REF (negative in the graphical case shown) is applied to the integrator 106 along with the input voltage V.sub.IN for several intervals of duration t.sub.1. The reference voltage V.sub.REF serves to slightly discharge V.sub.INT. The integrator output voltage V.sub.INT therefore has a slope proportional to V.sub.IN +V.sub.REF during such discharging intervals. The discharging intervals can be repeated as necessary to maintain the integrator output voltage V.sub.INT below the voltage V.sub.1. The total time t.sub.3 during which V.sub.REF is applied, which is equal to the sum of the discharging intervals having duration t.sub.1, is measured for use in calculating the unknown input voltage V.sub.IN. As indicated in FIG. 3, the magnitude of the input voltage V.sub.IN is calculated as follows: EQU V.sub.IN =(t.sub.3 *V.sub.REF +t.sub.2 *V.sub.REF)/T, where t.sub.3 ={t.sub.1 }
The discharging technique illustrated in FIG. 3 produces a multiplicative error due to switch time mismatch errors. These switch time mismatch errors are discussed in regard to FIG. 4. FIG. 4 illustrates the switching characteristics for a typical switch, for example, the switch 112, which is used to selectively couple the reference voltage V.sub.REF into the A/D converter. The ideal switching curve for a switch turned on at a time t.sub.1 and turned off at a time t.sub.2 is indicated by the dotted curve in FIG. 4. The solid curve shows the actual switch response in the real world. Because the turning-on and turning-off characteristics are typically not symmetric, the total ideal charge transfer proportional to the reference voltage V.sub.REF *(t.sub.2 -t.sub.1) will not equal the actual charge transfer. Because of the switching time mismatches, the switch is effectively held open for an additional switching mismatched time .DELTA.t (.DELTA.t can be positive or negative), thereby transferring a charge proportional to V.sub.REF *(t.sub.2 -t.sub.1 -.DELTA.t). In a switching scheme such as that shown in FIG. 3, where the number and switch activations is proportional to the magnitude of the input voltage V.sub.IN, such mismatch of switching times will produce an error in the A/D conversion proportional to n*.DELTA.t. The integer n is an integer valued step function increasing with the increase in the magnitude of the input voltage V.sub.IN and representing a coarse valuation of the input voltage V.sub.IN. The switching time mismatch error results in a multiplicative error in this coarse valuation of V.sub.IN.
To correct for this error, the A/D converter requires a scaling factor which adjusts the measured results before output of the digital result. Such adjustment requires the measurement of a known reference voltage to set the scaling factor, and then each subsequent measurement requires a multiplication of the coarse valuation of this scaling factor. Since subtractions are more easily and rapidly executed than multiplications, it would be advantageous to convert switched time mismatched scaling errors into offset errors which can be eliminated by subtraction.
U.S. Pat. No. 4,357,600 to Ressmeyer, which is incorporated herein by reference, discloses a multislope A/D converter for producing a digital indication of an input voltage. FIG. 5 substantially represents the embodiment taught by the Ressmeyer patent. In the Ressmeyer embodiment, positive and negative reference voltages V.sub.REF are selectively applied in order to maintain the integrator output voltage V.sub.INT within a particular voltage range, such as the bounds of the integrator power supply voltages (positive and negative).
As shown in FIG. 5, a positive reference voltage +V.sub.REF is continuously supplied to the A/D converter, while the negative reference voltage -V.sub.REF is supplied in accordance with the states of switches A and B. Effectively, the input voltage V.sub.IN can pass through to the integrator 106 unaffected, or can be manipulated by the positive reference voltage +V.sub.REF or the negative reference voltage -V.sub.REF. Specifically, when switch A connects ("1") the negative reference voltage -V.sub.REF to the A/D converter while the switch B disconnects ("0") the negative reference voltage -V.sub.REF, as shown in FIG. 5, the result is that the input voltage V.sub.IN enters the integrator 106 substantially unaffected. In other words, the current I.sub.2 cancels the current I.sub.1, while the current I.sub.3 approximately equals zero. The same circuit scenario ensues when switch A equals zero and switch B equals 1.
Moreover, in order to apply the positive reference voltage +V.sub.REF, both switches A and B are set to zero. Finally, to apply the negative reference voltage -V.sub.REF to the input voltage V.sub.IN, both switches A and B are set to 1.
The Ressmeyer patent teaches a four-step pattern, which is repeated as many times as is required, during the RU interval of the integrating A/D converter. The four-step pattern is set forth in Table A below.
TABLE A ______________________________________ Reference Origin of Voltage Bias State of State of Switch Step to V.sub.IN Switch A Switch B States ______________________________________ 1 zero 0 1 forced 2 +/- 0(1) 0(1) comparator driven 3 zero 1 0 forced 4 +/- 0(1) 0(1) comparator driven ______________________________________
As indicated in Table A, the first step is to permit the input voltage to enter the integrator 106 unaffected. The foregoing state is forced by the switches A and B, irrespective of the integrator output voltage V.sub.INT. The second step envisions applying either the positive reference voltage +V.sub.REF or the negative reference voltage -V.sub.REF to the input voltage. The second step is driven, or forced, by the comparator 108. Essentially, if the integrator output voltage V.sub.INT is at a positive voltage, the comparator 108 causes the control logic to apply the negative reference voltage -V.sub.REF. Conversely, if the integrator output voltage V.sub.INT is negative, the comparator 108 causes the control logic to apply the positive reference voltage +V.sub.REF.
In step 3, as shown in Table A, the input voltage V.sub.IN is again permitted to reach the integrator 106 unaffected. This step is forced by the control logic without regard to the integrator output voltage V.sub.INT. Finally, in step 4 of the four-step pattern, the input voltage V.sub.IN is affected by either the positive reference voltage +V.sub.REF or the negative reference voltage -V.sub.REF, depending upon the integrator output voltage V.sub.INT. In other words, the fourth step, just as the second step, is forced by the comparator 108.
FIG. 6 is a plot of a switch state versus pattern state in regard to FIG. 5. Essentially, FIG. 6 is a graphical representation of Table A above.
The four-step pattern disclosed by U.S. Pat. No. 4,357,600 has advantages. The repetition of the pattern can be used to confine any input voltage V.sub.IN within the bounds of any desired voltage limits, such as the operating voltage range of the integrator 106. Furthermore, the pattern causes the switching errors associated with the reference voltage -V.sub.REF to be an offset in the integrator 106, rather than an effect on the gain of the integrator 106. More specifically, if one considers the switching transitions of the switches A and B, it is readily apparent that for each sequence of the four-step pattern each of the switches A and B connects ("1") and then disconnects ("0") the negative reference voltage -V.sub.REF. Thus, a rising and falling transient is introduced by each switch. Hence, the foregoing transients substantially cancel each other with a slight offset. Worth noting is that the positive reference voltage +V.sub.REF is already a part of the offset of the integrator 106, because it is not switched at all.
Also worth noting is U.S. Pat. No. 4,951,053 to DesJardin, which is incorporated herein by reference. The DesJardin patent sets forth an improved integrating A/D converter for utilizing the four-step pattern disclosed in U.S. Pat. No. 4,357,600. Essentially, the improved circuit provides for reducing heat effects caused by the switches A and B. Also, the improved circuit stabilizes the reference voltages by way of switching currents, rather than voltages.